Integrated circuit memory devices are typically classified into two categories: random access memory (RAM) and read only memory (ROM) devices. Random access memory (RAM) devices are typically volatile memory devices that lose their data when power to the memory is interrupted. In contrast, read only memory (ROM) devices are typically non-volatile memory devices that retain their data even when power is interrupted. Examples of non-volatile memory devices include programmable ROM (PROM), erasable programmable ROM (EPROM) and electrically erasable programmable ROM (EEPROM). Flash memory devices may be classified into two groups, NOR flash and NAND flash, based on the type of logic gate used in each storage device.
In NAND flash memory devices, an erase operation is performed in block units. During an erase operation, a high voltage of about 20V is applied to the bulk, and an erase voltage of about 0V is applied to the gates of the memory cells. Electrons are injected from a floating gate to a channel by F-N tunneling. This operation is referred to as “erase operation”. As a result of an erase operation, NAND flash memory devices store data “1” to the memory cells.
In a conventional NAND flash memory device, during an erase operation, an erase voltage with the same level is applied to all word lines. A problem with this, however, is that the threshold voltage profile of the memory cells spreads so that different cells have different threshold voltages.
An erase operation is simultaneously performed with on all memory cells in a memory blocks. Preferably, memory cells that are simultaneously erased should have substantially equal channel lengths. However, due to limitations in semiconductor manufacturing processes, it is difficult to fabricate memory cells with equal channel lengths. If the memory cells have different channel lengths, they also have different capacitance coupling ratios during an erase operation. Variation in capacitance coupling ratios result in different erase speeds for different memory cells. As a result, the threshold voltage profile of the memory cells is spread after an erase operation.